U.S. note 39(b)
(b) For the purposes of this note, “semiconductor articles” refers to imported products meeting certain technical parameters and that are classifiable in the provisions of the HTSUS enumerated in this subdivision: 8471.50 8471.80 8473.30 To be included within the definition of semiconductor articles, the imported products must be a logic integrated circuit, or an article that contains a logic integrated circuit, that meets the technical parameters of having:
(1) a total processing performance greater than 14,000 and less than 17,500, and a total DRAM bandwidth greater than 4,500 GB/s and less than 5,000 GB/s; or
(2) a total processing performance greater than 20,800 and less than 21,100, and total DRAM bandwidth greater than 5,800 GB/s and less than 6,200 GB/s. For the purposes of this note, total processing performance (TPP) is 2 × “MacTOPS” × “bit length of the operation,” aggregated over all processing units on the integrated circuit. “MacTOPS” is the theoretical peak number of Tera (10 12 ) operations per second for multiply-accumulate computation (D = A × B + C). The 2 in the TPP formula is based on the industry convention of counting one multiply-accumulate computation (D = A × B + C) as two operations for purpose of product datasheets. Therefore, 2 × “MacTOPS” may correspond to the reported TOPS or FLOPS on a product datasheet. The “bit length of the operation” for a multiply-accumulate computation is the largest bit-length of the inputs to the multiply operation. The TPP for the imported product is determined by aggregating the TPP for each processing unit on the integrated circuit: TPP = TPP1 + TPP2 + … + TPPn (where n is the number of processing units on the integrated circuit). The rate of “MacTOPS” is to be calculated at its maximum value theoretically possible. The rate of “MacTOPS” is assumed to be the highest value the manufacturer claims in annual or brochure for the integrated circuit. For example, a “TPP” threshold of 4800 can be met with 600 tera integer operations (or 2 × 300 “MacTOPS”) at 8 bits or 300 tera FLOPS (or 2 × 150 “MacTOPS”) at 16 bits. If the integrated circuit is designed for MAC computation with multiple bit lengths that achieve different “TPP” values, the highest “TPP” value should be used. For integrated circuits that provide processing of both sparse and dense matrices, the “TPP” values are the values for processing of dense matrices (e.g., without sparsity). For the purposes of this note, “total DRAM bandwidth” refers to the aggregate memory bandwidth in gigabytes per second between the integrated circuit (IC) and dynamic random access memory (DRAM) ICs, including copackaged DRAM ICs and non-copackaged DRAM ICs. Copackaged DRAM ICs include, for example, high bandwidth memory (HBM). Non-copackaged DRAM ICs include, for example, graphics double data rate (GDDR) ICs. “Total DRAM bandwidth” does not include bandwidth from DRAM ICs accessed remotely over an interconnect medium.