9903.79.01

U.S. note 39(a)

(a) Except as provided for in headings 9903.79.02–9903.79.09, heading 9903.79.01 provides the ordinary customs duty treatment of semiconductor articles of all countries as described in subdivision (b) of the note. For any such products that are eligible for special tariff treatment under any of the free trade agreements or preference programs listed in general note 3(c)(i) to the tariff schedule, the duties provided in heading 9903.79.01 shall be collected in addition to any special rate of duty otherwise applicable under the appropriate tariff subheading. Goods for which entry is claimed under a provision of chapter 98 and that are subject to the additional duties prescribed herein shall be eligible for and subject to the terms of such provision and applicable U.S. Customs and Border Protection (CBP) regulations, except that duties under subheading 9802.00.60 shall be assessed based upon the full value of the imported article. No claim for entry or for any duty exemption or reduction shall be allowed for semiconductor articles enumerated in subdivision (b) of this note under a provision of chapter 99 that may set forth a lower rate of duty or provide duty-free treatment, taking into account information supplied by CBP, but any additional duty prescribed in any provision of this subchapter or subchapter IV of chapter 99 shall be imposed in addition to the duties in heading 9903.79.01. All antidumping, countervailing, or other duties and charges applicable to such goods shall continue to be imposed in addition to the duties in heading 9903.79.01, except that such articles shall not be subject to:

(1) the additional duties imposed on entries of passenger vehicles and light trucks under headings 9903.94.01, 9903.94.03, 9903.94.31, 9903.94.40, 9903.94.41, 9903.94.50, 9903.94.51, 9903.94.60 and 9903.94.61;

(2) the additional duties imposed on entries of parts for passenger vehicles and light trucks under headings 9903.94.05, 9903.94.07, 9903.94.32, 9903.94.33, 9903.94.42, 9903.94.43, 9903.94.44, 9903.94.45, 9903.94.52, 9903.94.53, 9903.94.54, 9903.94.55, 9903.94.62, 9903.94.63, 9903.94.64, 9903.94.65, 9903.94.66, 9903.94.67, 9903.94.68, and 9903.94.69;

(3) the additional duties imposed on entries of medium- and heavy-duty vehicles under headings 9903.74.01, 9903.74.02 and 9903.74.03;

(4) the additional duties imposed on entries of parts of medium- and heavy-duty vehicles under headings 9903.74.08 and 9903.74.09;

(5) the additional duties imposed on entries of articles of aluminum, of steel, or of copper or derivative aluminum or steel articles provided for in headings 9903.82.02 and 9903.82.04–9903.82.26;

(6) the additional duties imposed on entries of articles the product of Canada under heading 9903.01.10;

(7) the additional duties imposed on entries of articles the product of Mexico under heading 9903.01.01; and

(8) the additional duties imposed on entries of articles under headings 9903.01.24–9903.01.76 and 9903.02.01–9903.02.71.

U.S. note 39(b)

(b) For the purposes of this note, “semiconductor articles” refers to imported products meeting certain technical parameters and that are classifiable in the provisions of the HTSUS enumerated in this subdivision: 8471.50 8471.80 8473.30 To be included within the definition of semiconductor articles, the imported products must be a logic integrated circuit, or an article that contains a logic integrated circuit, that meets the technical parameters of having:

(1) a total processing performance greater than 14,000 and less than 17,500, and a total DRAM bandwidth greater than 4,500 GB/s and less than 5,000 GB/s; or

(2) a total processing performance greater than 20,800 and less than 21,100, and total DRAM bandwidth greater than 5,800 GB/s and less than 6,200 GB/s. For the purposes of this note, total processing performance (TPP) is 2 × “MacTOPS” × “bit length of the operation,” aggregated over all processing units on the integrated circuit. “MacTOPS” is the theoretical peak number of Tera (10 12 ) operations per second for multiply-accumulate computation (D = A × B + C). The 2 in the TPP formula is based on the industry convention of counting one multiply-accumulate computation (D = A × B + C) as two operations for purpose of product datasheets. Therefore, 2 × “MacTOPS” may correspond to the reported TOPS or FLOPS on a product datasheet. The “bit length of the operation” for a multiply-accumulate computation is the largest bit-length of the inputs to the multiply operation. The TPP for the imported product is determined by aggregating the TPP for each processing unit on the integrated circuit: TPP = TPP1 + TPP2 + … + TPPn (where n is the number of processing units on the integrated circuit). The rate of “MacTOPS” is to be calculated at its maximum value theoretically possible. The rate of “MacTOPS” is assumed to be the highest value the manufacturer claims in annual or brochure for the integrated circuit. For example, a “TPP” threshold of 4800 can be met with 600 tera integer operations (or 2 × 300 “MacTOPS”) at 8 bits or 300 tera FLOPS (or 2 × 150 “MacTOPS”) at 16 bits. If the integrated circuit is designed for MAC computation with multiple bit lengths that achieve different “TPP” values, the highest “TPP” value should be used. For integrated circuits that provide processing of both sparse and dense matrices, the “TPP” values are the values for processing of dense matrices (e.g., without sparsity). For the purposes of this note, “total DRAM bandwidth” refers to the aggregate memory bandwidth in gigabytes per second between the integrated circuit (IC) and dynamic random access memory (DRAM) ICs, including copackaged DRAM ICs and non-copackaged DRAM ICs. Copackaged DRAM ICs include, for example, high bandwidth memory (HBM). Non-copackaged DRAM ICs include, for example, graphics double data rate (GDDR) ICs. “Total DRAM bandwidth” does not include bandwidth from DRAM ICs accessed remotely over an interconnect medium.